1. Field of the Invention
The present invention relates to logic for controlling the transmission of data signals between a processor and its associated memory and input/output devices.
2. Prior Art
Through the utilization of LSI MOS technology the size and cost of processors have decreased manyfold. Accordingly it has become possible to construct an entire processor on a single LSI MOS chip. However, these devices suffer from the disadvantage of having a high circuit to pin ratio, meaning pins are at a premium. One method in the prior art sought to overcome this problem by using the same pins for input and output and using internal circuitry to switch the data between input and output buffers of the processor. With this arrangement the system is limited to performing input and output operations serially. That is, an input or output operation must be completed before the next input or output can take place. This degrades processor performance because the speed of operation of the processor is limited by the speed of the input and output device.
LSI MOS technology has also led to dramatic size and cost reductions in memory. In using this technology for memory application, there is a critical tradeoff between cost and speed of application. The faster the memory operates the larger the electronic devices with which the memory must be built -- hence the more expensive the memory. One of the key parameters by which the speed of the memory is measured is called access time. Access time is the time from which the memory is initially commanded to read the data at a certain address to which that data is availale from the memory. Typically in the prior art the address from which data is to be read, the reading of that data, and the transfer of the data into a register in the processor all take place within a period of time caled a machine cycle. Only after all of this has been accomplished can the address for the next read (or write) be specified to the memory and the next machine cycle commenced. The memory access time is, consequently, very critical to determining the speed with which the processor operates.